1. Field of the Invention
This invention relates to an insulated gate type semiconductor device, and particularly to the improvement of the structure of a thin-film insulated gate field effect transistor (TFT) and a method for producing the same.
2. Description of Related Arts
Recently, a thin-film insulated gate field effect transistor (TFT) has been extensively studied. For example, in Japanese Patent Application No. 3-237100 or No. 3-238713 which has been invented by this inventor, et.al., are disclosed a TFT and a method of producing the same in which a gate electrode formed of aluminum is coated therearound with aluminum oxide which is formed by an anodic oxidation method, and a source/drain region is recrystallized by a laser annealing treatment.
The TFT thus formed has been proved to have a more excellent characteristic in comparison with a conventional silicon gate TFT or a TFT having a gate electrode which is formed of metal having high melting point such as tantalum or chrome. However, this excellent characteristic has been unobtainable with high reproducibility.
In addition, in Japanese Patent Application No. 4-30220 or No. 4-38637 which is invented by the inventor, et.al, is disclosed another type TFT and a method for producing the TFT in which a gate electrode formed of aluminum, titanium, chrome, tantalum or silicon is coated therearound with aluminum oxide formed by the anodic oxidation method so that the source/drain is not overlapped with the gate electrode, that is, these elements are formed in an offset state, and the source/drain region is recrystallized by the laser annealing treatment.
The TFT thus formed is also proved to have a more excellent characteristic in comparison with a conventional silicon gate TFT having no offset or a TFT which is provided with a gate electrode formed of metal having high melting point such as tantalum or chrome and is activated by a heat annealing treatment. However, this excellent characteristic has been also unobtainable with high reproducibility. One cause of the low reproducibility resides in the invasion (contamination) of movable ions such as natrium, etc. from the external. The reproducibility is deteriorated by the invasion of natrium from the external, particularly in a process of forming a gate electrode of metal material such as aluminum or the like (using a sputtering method or a electron beam deposition method), and in a subsequent anodic oxidation process. Particularly in the sputtering method, the risk of the invasion (contamination) of natrium ions is large. However, the sputtering method has higher producibility than the electron beam deposition method, and thus its use has been necessarily desirable to reduce a manufacturing cost.
It has been known that natrium is blocked by phosphosilicate glass and also gettered thereby. Therefore, a gate insulating film has been generally formed of phosphosilicate glass. However, it is difficult to form the phosphosilicate glass at a low temperature which is aimed by the inventions as disclosed in the above Patent Applications. In addition, if the formation of the phosphosilicate glass at such a low temperature is attempted, for example by injecting phosphorus into a silicon oxide gate insulating film using an ion doping method, there frequently occurs a problem that a large number of defects occur in the gate insulating film and thus the characteristic of the TFT is rather deteriorated.
In addition, high voltage of 100 to 300 V is required for the anodic oxidation, and thus there is a risk that the gate insulating film is damaged by the high voltage. That is, in the technical scope of the inventions as described above, the gate insulating film is formed on a semiconductor film, and the gate electrode exists on the gate insulating film. In this construction, a voltage occurs between the positively-charged gate electrode and the semiconductor film in a floating state in the anodic oxidation process. Therefore, as the resistance between the gate electrode and an electrolyte is increased in accordance with increase of the thickness of an anodic oxidation film on the gate electrode, the amount of current passing from the gate electrode through the gate insulating film and the semiconductor film to the electrolyte is increased. Accordingly, there occurs a case where the gate electrode is damaged by this current.
Further, in the inventions as described above, aluminum oxide is formed around a gate wiring. The aluminum oxide serves to improve insulation from a wiring layer thereon, and protect the gate electrode in a laser annealing treatment. However, it is difficult to form a contact hole in the aluminum oxide. In addition, when aluminum oxide is etched by a wet etching method which is excellent in producibility, an etchant forcedly etches silicon oxide which is used as an interlayer insulator, and the etching rate of silicon oxide is higher than aluminum oxide. Therefore, a vapor etching method such as a reactive ion etching method is necessarily required to be used.
The TFT is mainly classified into an inverse-stagger type which is well used for an amorphous silicon TFT and a planar type which is well used for a polycrystal silicon TFT. The latter type can have large mobility, so that it is expected to be available for a wide use. Such a TFT is mainly used for a large-area circuit which has not been covered by a conventional monocrystal IC. The conventional planar type of TFT has the same construction as the conventional monocrystal IC as shown in FIG. 12.
As is apparent from FIG. 12, the planar type of TFT is so designed as to be very flat over its whole body. This structure is very favorable for a case where it is used as an active element for a liquid crystal display device. This is because in the liquid crystal display device, the thickness of a liquid crystal layer is about 5 to 6 .mu.m, and it is required to control the thickness with accuracy of .+-.0.1 .mu.m as a whole. Therefore, an element structure having high unevenness (a large number of recesses and projections) causes ununiformity of electric field, so that not only the characteristic of the element is deteriorated, but also the element itself suffers a mechanical damage.
The element structure as shown in FIG. 12 is a general one for the planar type of TFT. The structure and the method for producing the TFT will be briefly described.
A silicon oxide layer 902 serving as a sealer is formed on an insulating substrate 901 such as a glass substrate, and a semiconductor region 903 is formed on the silicon oxide layer 902. Further, a gate insulating film 904 is formed, and then a wiring 905 and a gate electrode 906 are formed of a first metal wiring layer.
Thereafter, an impurity region is formed in the semiconductor region in self-alignment, an interlayer insulator 907 is formed, and then a hole for electrode formation (contact hole) is formed. Subsequently, metal wirings 908 and 909 are formed of a second metal wiring layer. If the TFT is used for a liquid crystal display device, a pixel electrode 910 is formed of transparent conductive material.
As described above, the planar type of TFT having the structure as shown in FIG. 12 is characterized in that unevenness of the structure is low, however, has several problems. The maximum significant problem resides in that a hole is formed in an electrode, and thus unevenness becomes higher at the contact hole portion, so that disconnection or contact failure occurs at the portion. Particularly, an unit part of a large-area circuit in which a TFT is used, has an area of at least 10 times as large as a conventional monocrystal IC, so that it is very difficult to depress the disconnection or contact failure over the whole area. In order to avoid this problem, the contact hole is required to be widened. However, the increase of the size of the contact hole causes enlargement of the element area, and causes reduction in aperture ratio for a liquid crystal display device, for example.
In order to further avoid this problem, a structure as shown in FIG. 11 in which the concept of "contact hole" is dismissed and the unevenness at the electrode portion is depressed is proposed. In this structure, there is no interlayer insulator at an electrode portion which is connected to a source/drain of a semiconductor region, and no contact hole is provided. In place of the contact hole, a metal wiring is directly formed. This structure enables the contact area of the contact to be increased, and the contact failure at the portion is greatly reduced. This is based on the fact that there is little step at the contact portion.
The structure as shown in FIG. 11 and the method of producing the structure will be briefly described.
First, a silicon oxide layer 802 serving as a sealer is formed on a substrate 801. Subsequently, a semiconductor region 803 is formed, and then a gate insulating film 804 is formed. Further, a wiring 805 and a gate electrode 806 are formed of a first metal layer, and an impurity region is formed in self-alignment using the gate electrode as a mask, thereafter, an interlayer insulator 807 being formed. The interlayer insulator 807 is not formed at the semiconductor region. For example, after the layer insulating film is formed over the whole surface, the layer insulator at the semiconductor region is removed. At this time, the gate insulating film 804 is also etched. In an extreme manner, no interlayer insulator is formed at portions other than a portion where the first and second metal layers are overlapped with each other. That is, the etching treatment is carried out in self-alignment using the gate electrode 806 and the semiconductor region 803 as a mask together with a photoresist at the portion where wirings are intersected to each other. Thereafter, wirings 808 and 809 are formed of the second metal layer, and contacted to the semiconductor region. For the liquid crystal display device, a transparent electrode 810 is further formed.
In the structure as shown in FIG. 11, there is no contact hole, and thus no contact failure occurs at this portion. However, other problems occur. One problem is that in a process of removing the interlayer insulating film, the etching extends to not only the silicon oxide film 802, but also the substrate. This is liable to occur when the etching process is carried out using the wet etching method providing high producibility. The temperature distribution of the substrate of a large-area substrate is ununiform, and the etching rate of an usual etchant is greatly varied in accordance with minute difference of temperature, so that an over-etched portion occurs when the etching treatment is continued until the etching is completely conducted on the whole portion.
On the other hand, in a dry etching treatment such as a reactive ion etching (RIE), the uniformity of plasma distribution greatly affects the etching rate, and it is difficult to assure uniformity of etching over the whole area of the substrate. Therefore, the larger the area is, the more critical the over-etching problem becomes. For example, as shown in FIG. 11, there occurs a case where the substrate is etched in depth of d due to an over-etch. This structure has a larger step than the structure as shown in FIG. 12, and thus it is unsuitable not only for the liquid crystal display device, but also for other applications such as a driving circuit for an image sensor, etc.
In addition, even on the same substrate, no over-etch occurs at suitably-etched portions, and thus these portions are not etched as shown above. Therefore, the etching depth is varied with a position on the surface of the substrate, so that a moderate unevenness occurs on the surface of the substrate. This unevenness on the surface of the substrate causes a critical problem for application to the liquid crystal display device.
The over-etching problem is not limited to the above problem. In general, a semiconductor element is formed under an extremely pure atmosphere, and foreign elements such as natrium, etc. are extremely excluded. However, foreign elements are necessarily contaminated in the substrate although contamination amount is varied, and in order to prevent diffusion of the foreign elements in the TFT, these elements are blocked by the silicon oxide film layer serving as a sealer.
However, the above blocking effect of the silicon oxide layer would be lost if the substrate is exposed due to the over-etch as shown in FIG. 11, and thus the foreign elements are diffused through the substrate. The foreign elements contaminate an etching tank for the wet etching treatment, or an etching chamber for the dry etching treatment, for example. Therefore, if the contaminated state is left as it is, the contamination would extend to not only a product concerned, but also other products to be subsequently manufactured. Much labor and long time are required for a cleaning process for removing the foreign elements, and such a special process economically deteriorates this method.